Computers use a clock multiplier to multiply lower frequency external clock signals to high frequency clock signals. Such multipliers may be used to allow microprocessors or a portion thereof to operate at a higher frequency than other parts of a system. Alternatively, a high frequency clock signal for microprocessors may be divided down to a lower frequency to cater for operations of input/output buses, such as, for example, SATA (Serial ATA), AGP (Accelerated Graphics Port), PCI-E (Peripheral Component Interconnect Express), SCSI (Small Computer System Interface). In general, integrated circuits utilize a clock signal in order to synchronize different parts of the IC.
Overclocking occurs when setting a computer component (e.g., a microprocessor) to run at a higher clock frequency than it is designated by the manufacturer. Some manufacturers conduct testing under an overclocking environment to determine the safety margins of components under different operating conditions. Underclocking, also known as downclocking, occurs when modifying the operating frequency of a synchronous circuit to run at a lower clock frequency than the specification. Conventional circuits perform overclocking or underclocking by modifying a divider/multiplier ratio of a clock generation circuit. The clock frequency changes abruptly whenever a new divider/multiplier ratio is set. As a result, the circuits have to shut down or use an alternative clock signal, while the clock signal is being changed, to avoid potential erroneous operations.
Phase locked loop are commonly used to generate clock signals for use in computer systems. Some phase locked loop designs incorporate a phase interpolator circuit to fine-tune the phase value of the output clock. For such designs, the phase setting of the phase interpolator circuit remains unchanged if the targeted phase value is obtained after a fine-tuning process.